The invention relates to inspection of integrated circuits, and more particularly to inspection of integrated circuits using photo-emissions.
The semiconductor industry has seen tremendous advances in technology in recent years, permitting dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of tens (or even hundreds) of MIPS (millions of instructions per second) to be packaged in relatively small, air-cooled semiconductor device packages. A by-product of such high-density and high functionality in semiconductor devices has been the demand for increased numbers of external electrical connections to be present on the exterior of the die and on the exterior of the semiconductor packages which receive the die, for connecting the packaged device to external systems, such as a printed circuit board.
Typically, dies contain a bonding pad which makes the electrical connection to the semiconductor package. To shorten the electrical path to the pad, another packaging technology called flip-chip packaging is employed, where the pads were moved to the side of the die nearest the transistors and other circuit devices formed in the die. Connection to the package is made when the chip is flipped over and soldered. As a result, the dies are commonly called flip chips in the industry. Each bump on a pad connects to a corresponding package inner lead. The packages which result are lower profile and have lower electrical resistance and a shortened electrical path. The plurality of ball-shaped conductive bump contacts (usually solder, or other similar conductive material) are typically disposed in a rectangular array. The packages are occasionally referred to as xe2x80x9cBall Grid Arrayxe2x80x9d (BGA) or xe2x80x9cArea Grid Arrayxe2x80x9d packages.
FIG. 1 is a cross-sectional view of an example BGA device 10. The device 10 includes an integrated circuit 12 mounted upon a larger package substrate 14. Substrate 14 includes two sets of bonding pads: a first set of bonding pads 16 on an upper surface adjacent to integrated circuit 12 and a second set of bonding pads 18 arranged in a two-dimensional array across an underside surface. Integrated circuit 12 includes a semiconductor substrate 20 having multiple electronic components formed within a circuit layer 22 upon a front side surface of semiconductor substrate 20 during wafer fabrication. The back side surface 23 remains exposed after the device 10 is formed. The electronic components are connected by electrically conductive interconnect lines to form an electronic circuit. Multiple I/O pads 24 are also formed within circuit layer 22. I/O pads 24 are typically coated with solder to form solder bumps 26.
The integrated circuit is attached to the package substrate using the controlled collapse chip connection method, which is also known as the C4(copyright) or flip-chip method. During the C4 mounting operation, solder bumps 26 are placed in physical contact with corresponding members of the first set of bonding pads 16. Solder bumps 26 are then heated long enough for the solder to reflow. When the solder cools, I/O pads 24 of integrated circuit 12 are electrically and mechanically coupled to the corresponding members of the first set of bonding pads 16 of the package substrate. After integrated circuit 12 is attached to package substrate 14, the region between integrated circuit 12 and package substrate 14 is filled with an under-fill material 28 to encapsulate the C4 connections and provide additional mechanical benefits.
Package substrate 14 includes one or more layers of signal lines that connect respective members of the first set of bonding pads 16 and the second set of bonding pads 18. Members of the second set of bonding pads 18 function as device package terminals and are coated with solder, forming solder balls 30 on the underside surface of package substrate 14. Solder balls 30 allow BGA device 10 to be surface mounted to an ordinary PCB. During PCB assembly, BGA device 10 is attached to the PCB by reflow of solder balls 30 just as the integrated circuit is attached to the package substrate.
The C4 mounting of integrated circuit 12 to package substrate 14 prevents physical access to circuit layer 22 for failure analysis and fault isolation. Thus, new approaches that are efficient and cost-effective are required.
It is well known that CMOS transistors emit photons during a state change, for example, switching the gate of a transistor. Photons are emitted from transistors at pn junctions, for example. These transient events occur on time scales that are less than 100 ps. Thus, in order to record these events, a very fast detector is required. In addition, a very sensitive detector is required for observing very weak emissions through the backside of the semiconductor because of the absorption losses in the silicon substrate. Another aspect of the emission analysis is to spatially resolve the emissions. It is desired to detect emissions from a single transistor where the device dimensions may be sized less than a micron. Therefore, an apparatus and method that provides fast and cost effective spatially and temporally resolved photoemission analysis of semiconductor circuits is desirable.
In various embodiments, methods and systems are provided for single point high resolution time resolved photoemission microscopy for an integrated circuit. In one embodiment, an apparatus is provided for analyzing an integrated circuit to which test signals are applied. The apparatus comprises a microscope, an aperture element, and a photo-diode. The microscope has an objective lens that forms a focal plane and is arranged to view the integrated circuit; the aperture element has an aperture which is optically aligned in the focal plane of the microscope; and the aperture element is positioned for viewing a selected area of the integrated circuit. The photo-diode is optically aligned with the aperture to detect photoemissions when test signals are applied to the integrated circuit.
In another embodiment, a process is provided for analyzing an integrated circuit with a microscope having a focal plane behind an objective lens. The process comprises placing an aperture element having an aperture in the focal plane of the objective lens of the microscope and positioning the aperture for viewing a selected area of the integrated circuit. A photo-diode is optically aligned with the aperture, and the integrated circuit is placed in view of the microscope. Test signals are applied to the integrated circuit, and a photo-emission is detected from the selected area of the integrated circuit.
The above summary is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and the detailed description which follow more particularly exemplify these embodiments.